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Philips Semiconductors

ISP1581

USB 2.0 HS interface device

Objective speciﬁcation Rev. 02 — 23 October 2000 31 of 73

9397 750 07648

[1] Nibble = 4 bits. MSN: Most Signiﬁcant Nibble, LSN: Least Signiﬁcant Nibble.

9.4.5 DMA Strobe Timing register (address: 60H)

This 1-byte register controls the strobe timings for UDMA and MDMA mode, when the

UDMA_MODE bits in the DMA Conﬁguration register have been set to 03H. The bit

allocation is given in Table 39 .

Table 37: DMA Hardware register: bit allocation (modes GDMA, MDMA (Master) and MDMA (ATA) only)

Bit 7 6 5 4 3 2 1 0

Symbol ENDIAN[1:0] EOT_

POL

MASTER ACK_

POL

DREQ_

POL

WRITE_

POL

READ_

POL

Reset 00H 000100

Bus reset 00H 000100

Access R/W R/W R/W R/W R/W R/W R/W

Table 38: DMA Hardware register: bit description

Bit Symbol Description

7 to 6 ENDIAN[1:0] These bits determine whether the data bus is swapped between

internal RAM and the DMA bus: nibbles

[1]

(8-bit bus) or bytes

(16-bit bus). This only applies for modes GDMA (slave) and

MDMA (master).

00H — normal data representation

8-bit bus: MSN on DATA[7:4], LSN on DATA[3:0];

16-bit bus: MSB on DATA[15:8], LSB on DATA[7:0]

01H — swapped data representation

8-bit bus: MSN on DATA[3:0], LSN on DATA[7:4];

16-bit bus: MSB on DATA[7:0], LSB on DATA[15:8]

02H, 03H — reserved.

5 EOT_POL Selects the polarity of the End Of Transfer input (used in GDMA

slave mode only):

0 — EOT is active LOW

1 — EOT is active HIGH.

4 MASTER Selects the DMA master/slave mode:

0 — GDMA slave mode.

1 — MDMA master mode.

3 ACK_POL Selects the DMA acknowledgement polarity:

0 — DACK is active LOW

1 — DACK is active HIGH.

2 DREQ_POL Selects the DMA request polarity:

0 — DREQ is active LOW

1 — DREQ is active HIGH.

1 WRITE_POL Selects the DIOW strobe polarity.

0 — DIOW is active LOW

1 — DIOW is active HIGH.

0 READ_POL Selects the DIOR strobe polarity.

0 — DIOR is active LOW

1 — DIOR is active HIGH.

1 2 ... 26 27 28 29 30 31 32 33 34 35 36 ... 72 73

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